/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2023 Horizon Robotics Co,. Ltd
 */
#ifndef __ASM_ARCH_HORIZON_STRAPPIN_H__
#define __ASM_ARCH_HORIZON_STRAPPIN_H__
/****SYS STRAP PIN CFG REGS ****/
#define BOOT_STRAP_PIN_REG       (0x3E0A00A4)
#define BOOT_STRAP_PIN_OFFSET    (0xA4)
#define BOOT_MODE_SHIFT          (0)
#define BOOT_MODE_MASK           (7L << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_UART      (0 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_EMMC      (1 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_USB2      (2 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_SD        (3 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_QSPI_NOR  (4 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_QSPI_NAND (5 << BOOT_MODE_SHIFT)
#define PLAT_HORIZON_BOOT_SRC_USB3      (6 << BOOT_MODE_SHIFT)
#define BOOT_FORCE_SECURE_SHIFT  (3)
#define BOOT_FORCE_SECURE_MASK   (1L << BOOT_FORCE_SECURE_SHIFT)
#define BOOT_UART_BPS_SHIFT      (4)
#define BOOT_UART_BPS_MASK       (1L << BOOT_UART_BPS_SHIFT)
#define BOOT_FASTBOOT_SEL_SHIFT  (5)
#define BOOT_FASTBOOT_SEL_MASK   (1L << BOOT_FASTBOOT_SEL_SHIFT)
#define BOOT_DISABLE_WDOG_SHIFT  (6)
#define BOOT_DISABLE_WDOG_MASK   (1L << BOOT_DISABLE_WDOG_SHIFT)
#define BOOT_DISABLE_LOG_SHIFT   (7)
#define BOOT_DISABLE_LOG_MASK    (1L << BOOT_DISABLE_LOG_SHIFT)
#define BOOT_SKIP_CHECKSUM_SHIFT (8)
#define BOOT_SKIP_CHECKSUM_MASK  (1L << BOOT_SKIP_CHECKSUM_SHIFT)
#define BOOT_USB_BYPASS_SHIFT    (10)
#define BOOT_USB_BYPASS_MASK     (1L << BOOT_USB_BYPASS_SHIFT)
/* Nor BOOT CFG */
#define BOOT_NOR_CFG_ADDRESS_MODE_SHIFT (11)
#define BOOT_NOR_CFG_ADDRESS_MODE_MASK  (1L << BOOT_NOR_CFG_ADDRESS_MODE_SHIFT)
#define BOOT_NOR_CFG_CLK_RATE_SHIFT     (12)
#define BOOT_NOR_CFG_CLK_RATE_MASK      (3L << BOOT_NOR_CFG_CLK_RATE_SHIFT)
#define BOOT_NOR_CFG_RESET_SHIFT        (14)
#define BOOT_NOR_CFG_RESET_MASK         (1L << BOOT_NOR_CFG_RESET_SHIFT)
/* eMMC BOOT CFG */
#define BOOT_eMMC_CFG_CLK_LATCH_SHIFT   (11)
#define BOOT_eMMC_CFG_CLK_LATCH_MASK    (1L << BOOT_eMMC_CFG_CLK_LATCH_SHIFT)
#define BOOT_eMMC_CFG_CLK_RATE_SHIFT    (12)
#define BOOT_eMMC_CFG_CLK_RATE_MASK     (3L << BOOT_eMMC_CFG_CLK_RATE_SHIFT)
#define BOOT_eMMC_CFG_DATA_WIDTH_SHIFT  (14)
#define BOOT_eMMC_CFG_DATA_WIDTH_MASK   (1L << BOOT_eMMC_CFG_DATA_WIDTH_SHIFT)
#define BOOT_eMMC_CFG_SECTION_SEL_SHIFT (15)
#define BOOT_eMMC_CFG_SECTION_SEL_MASK  (3L << BOOT_eMMC_CFG_SECTION_SEL_SHIFT)
/* SD BOOT CFG */
#define BOOT_SD_CFG_CLK_LATCH_SHIFT  (11)
#define BOOT_SD_CFG_CLK_LATCH_MASK   (1L << BOOT_SD_CFG_CLK_LATCH_SHIFT)
#define BOOT_SD_CFG_CLK_RATE_SHIFT   (12)
#define BOOT_SD_CFG_CLK_RATE_MASK    (3L << BOOT_SD_CFG_CLK_RATE_SHIFT)
#define BOOT_SD_CFG_DATA_WIDTH_SHIFT (14)
#define BOOT_SD_CFG_DATA_WIDTH_MASK  (1L << BOOT_SD_CFG_DATA_WIDTH_SHIFT)
/* Nand BOOT CFG */
#define BOOT_NAND_CFG_PAGE_SIZE_SHIFT (11)
#define BOOT_NAND_CFG_PAGE_SIZE_MASK  (1L << BOOT_NAND_CFG_PAGE_SIZE_SHIFT)
#define BOOT_NAND_CFG_CLK_RATE_SHIFT  (12)
#define BOOT_NAND_CFG_CLK_RATE_MASK   (3L << BOOT_NAND_CFG_CLK_RATE_SHIFT)
#define BOOT_NAND_CFG_RESET_SHIFT     (14)
#define BOOT_NAND_CFG_RESET_MASK      (1L << BOOT_NAND_CFG_RESET_SHIFT)
#define BOOT_NAND_CFG_DUMMY_ID_SHIFT  (15)
#define BOOT_NAND_CFG_DUMMY_ID_MASK   (1L << BOOT_NAND_CFG_DUMMY_ID_SHIFT)
#define BOOT_NAND_CFG_PLANES_SHIFT    (16)
#define BOOT_NAND_CFG_PLANES_MASK     (1L << BOOT_NAND_CFG_PLANES_SHIFT)

#define BOOT_SRC_QSPI_NOR   0x4
#define BOOT_SRC_QSPI_NAND  0x5
#endif